The invention relates to a test system integrated on a substrate for the measurement and/or testing of parameters of test structures, an arbitrary one of the various test structures being connectable to the same externally accessible connection terminals by means of a multiplex circuit. The invention also relates to a method for using such a test system.
An integrated test system of this kind is known from a publication of the IEEE VLSI Workshop on Test Structures, held in Long Beach, Calif., Feb. 17 and 18, 1986. This publication by A. Nishimura et al, entitled "Multiplex Test Structure; a Novel VLSI Technology Development Tool", describes how the number of connection terminals for the measurement and/or testing of parameters of test structures included in a process control module can be limited. To this end, use is made of a multiplex circuit whereto ten external selection signals are applied, enabling the selection of 1024 different test structures. Using the multiplex circuit, a selected test structure is connected to some further connection terminals whereto supply voltages/stimuli are applied, the response of the test structure to the stimulus presented being measured on other connection terminals. According to said publication the test structures and the multiplex circuit are accommodated in a so-called test chip which is used for the development of new CMOS technology and/or new CMOS circuits. When a technique of this kind is used for monitoring the production process, several process control modules would have to be distributed across the semiconductor wafer to be processed. These process control modules then occupy substrate surface area which can normally be used for producing integrated semiconductor circuits. The foregoing reduces the yield of a silicon wafer. Therefore, it has been proposed (in the magazine Solid-State Technology, May 1985) to abstain from accommodating process control modules in the location of semiconductor circuits to be produced, and to arrange control modules/test circuits in the kerf areas surrounding the semiconductor circuits. Even though it is assumed in the cited publication that the kerf areas have a width of 200 .mu.m, they are much narrower in practice. Therefore, the number of connection terminals of test circuits must be minimized because these connection terminals have comparatively large dimensions of from 80.times.80 to 125.times.125 .mu.m.sup.2.